A 2Mbps circuit provides high
speed, digital transmission for voice, data, and video signals at 2.048 Mbps.
2.048 Mbps transmission systems are based on the ITU-T specifications G.703,
G.732 and G.704, and are predominant in
Europe, Australia, Africa, South America,
and regions of Asia. The 2.048 Mbps standards are now firmly established for
transmission systems and are used by telecommunications network suppliers,
international carriers and end users. The primary use of the 2.048 Mbps is in
conjunction with multiplexers for the transmission of multiple low speed voice
and data signals over one communication path rather then over multiple paths. Figure 1 shows a typical system.
The
2.048 Mbps Line Code
The
most common line code used to transmit the 2.048 Mbps signal is known as HDB3
(High Density Bipolar 3) which is a bipolar code with a specific zero
suppression scheme where no more then three consecutive zeros are allowed to
occur. The HDB3 line code is recommended for 2.048 Mbps signals by ITU-T
Recommendations G.703,
and
it is defined in Annex A to Recommendations G.703. In some instances
straightforward bipolar AMI (Alternate Mark Inversion) coding with no zero
suppression is also encountered. In the following paragraphs, we will first
review the AMI coding format, which represents the simplest version of bipolar
line code. We will then move on to
explaining
the 2.048 Mbps HDB3 line code, which essentially is a variation of AMI where a
high density of pulses is ensured by applying a zero suppression algorithm.
AMI
or Bipolar Line Code
In
the AMI coding format, a binary one (mark) is represented by a square pulse
with a 50% duty cycle and a binary zero (space) is represented by the lack of
pulse, i.e., 0 Volts. Since successive pulses (i.e., marks) alternate in
polarity the line code is termed AMI (Alternate Mark Inversion).
HDB3 Line Code
Despite its numerous advantages,
AMI coding has one very significant shortcoming. Since signal transition are
the
only way for 2.048 Mbps equipment
to recover the timing information, long strings of zeros with no pulse
transition in the data stream may cause the equipment to lose timing. Hence AMI
coding puts strict limitations on the zero content of the data transmission in
the 2.048 Mbps system. One solution to this problem is to use a coding scheme
that suppresses long string of zeros by replacing them with a specific sequence
of pulses, which can be recognised and decoded as zeros by 2.048 Mbps
equipment. HDB3 is one such coding scheme upon which the 2.048 Mbps industry standardized.
How
HDB3 Works
The
HDB3 signal is a bipolar signal, where sets of 4 consecutive zeros are replaced
by a specific sequence of pulses and the last pulse is coded as a violation.
This ensures that the 2.048 Mbps signal has a high density of pulses and no
more then 3 consecutive zeros. Table
1 shows the rules for zero
substitution using the HDB3 coding scheme.
An
example of how these rules are applied to an AMI signal is shown in Figure 2.
It
is important to note that:
1.
The 4th zero is always coded as a violation pulse.
2.
The 1st zero may be coded as a “balancing” pulse to ensure that successive HDB3
violation pulses are of opposite polarity, so that the net DC component of the
signal remains zero. Hence the HDP3 code eliminates all
the limitations on the zero content of the signal transmitted in the 2.048 Mbps
system, while preserving all the advantages of AMI coding.
Table 1:HDB3 substitution
rules
The
2.048 Mbps Framing Format
The 2.048 Mbps signal typically
consists of multiplexed data and/or voice which requires a framing structure
for
receiving equipment to properly
associate the appropriate bits in the incoming signal with their corresponding
channels.
Figure 3 shows the framing for the 2.048
Mbps signal as defined in ITU-T Recommendation G.704.
As can be seen in Figure 3, the 2.048 Mbps frame is broken
up into 32 timeslots numbered 0-31. Each timeslot contains 8 bits in a frame,
and since there are 8000 frames per second, each time slot corresponds to a
bandwidth of 8 x 8000 = 64 kbps.
Time slot 0 is allocated entirely
to the frame alignment signal (FAS) pattern, a remote alarm (FAS Distant Alarm)
indication bit, and other spare bits for international and national use. The
FAS pattern (0011011) takes up 7 bits (bits 2-8) in timeslot 0 of every other
frame. In those frames not containing the FAS pattern, bit 3 is reserved for
remote alarm indication (FAS Distant Alarm) which indicates loss of frame alignment
when it is set to 1. The remaining
bits in timeslot 0 are allocated
as shown in Figure 4.
If the 2.048 Mbps signal carries
novoice channels, there is no need to allocate additional bandwidth to
accommodate
signalling. Hence, time slot 1-31
are available to transmit data with an aggregate bandwidth of 2.048 Mbps - 64
kbps (TSO) = 1.984 Mbps.
If there are voice channels on the
2.048 Mbps signal, it is necessary to take up additional bandwidth to transmit
the
signalling information. ITU-T
Recommendation G.704 allocates time slot 16 for the transmission of the
channel- associated signalling information. This is explained in the next section.
The 2.048 Mbps TS-16 Multiframe Format
The 2.048 Mbps can carry up to
thirty 64 kbps voice channels in time slot 1-15 and 17-31. Voice
channels are numbered 1-30; voice channels 16-30 are carried in time slot
17-31. However,
the 8 bits in time slot 16 are
not
sufficient for all 30 channels to signal in one frame. Therefore, a multiframe
structure is required where channels can take turns using time slot 16. Since
two channels can send their ABCD signalling bits in each frame, a total
of
15 frames are required to cycle through all of the 30 voice channels. One
additional frame is required to transmit the multiframe alignment signal (MFAS)
pattern, which allows receiving equipment to align the appropriate ABCD
signalling bits with their corresponding voice channels. This results in the
TS-16 multiframe structure where each
multiframe
contains a total of 16 2.048 Mbps, numbered 0-15. Figure 4 on the previous page shows the
TS-16 multiframe format for the 2.048 Mbps signal as defined by the ITU-T
Recommendation G.704. As can be seen in Figure 4,
time slot 16 of frame 0 contains the 4-bit long multiframe alignment signal
(MFAS) pattern (0000) in bits 1-4. The “Y” bit is reserved for the remote alarm
(MFAS Distant Alarm) which indicates loss of multiframe alignment when it is
set to 1. Time slot 16 of frames 1-15 contains the ABCD signalling bits of the
voice channels.
Time slot 16 of the nth frame
carries the signalling bits of the nth and (n+15)th voice channels. For
example, frame 1 carries the signalling bits of voice channels 1 and 16, frame
2 carries the signalling bits of channels 2 and 17 etc.
It is also important to note that
the frame alignment signal (FAS) is transmitted in time slot 0 of the even
numbered frames. We have thus explained how frame alignment and channel
associated signaling are achieved in 2.048 Mbps transmission. (Alternatively,
time slot 16 may also be used for common channel signalling applications such
as primary rate ISDN). It must be noted, however, that the 2.048 Mbps framing
and TS-16 multiframing structures discussed so far do not provide any built in
error detection capabilities, which could be used to determine the error
performance of the 2.048 Mbps system on an in-service basis. This capability is
provided by the CRC (Cyclic Redundancy Check) multiframe structure as explained
in the next section.
The
2.048 Mbps CRC Multiframe Format
This section describes the
specifics of the 2.048 Mbps CRC Multiframe format. To find out how CRCs provide
the enhanced error performance monitoring capabilities mentioned above, refer
to the “CRC Error Analysis” section (page 9) under Application #1, In-Service
Analysis of Live Traffic. The 2.048 Mbps CRC Multiframe structure as defined by
ITU-T Recommendation G.704 is shown in Figure 5 on
the previous page.
and SMF-11) of 8 frames each. The
4-bit long CRC word associated with each submultiframe, SMF(N) is inserted into
the next sub-multiframe, SMF(N+1). The CRC bits take up the 1st bit of time
slot 0s containing the 7-bit FAS (Frame Alignment Signal) pattern. The CRC
Multiframe alignment signal uses the 1st bit of time slot 0s not containing the
FAS pattern. (See Figure 5).
Combining
the TS-16 and CRC Multiframe Structures
A 2.048 Mbps signal may come in a
number of different formats, depending on which of the above frame and
multiframe structures are implemented in the 2.048 Mbps system. Table 2 gives a comparison of the possible
variations of a 2.048 Mbps signal.
Causes
of 2.048 Mbps Impairments
Here are four main causes of 2.048
Mbps impairments:
1. Faulty
Equipment: Any piece of 2.048 Mbps equipment
can cause errors when the components
fail or operate outside of specifications. Errors, which can signal faulty
equipment, include code errors, bit errors, FAS (frame) errors, excessive
jitter, and slips. For instance, code errors can occur due to faulty clock
recovery circuitry in span repeaters. These errors occur as the equipment becomes
older and begins to drift out of specifications.
2. Improper
Connections: Transmission errors are created by
improper connections or configurations. For example,intermittent errors can
occur when component or cable connections are loose, and timing errors can
occur when improper or conflicting timing sources are connected together.
Dribbling errors are often caused by loose or unconnected shield ground cables
and by bridge taps. Further, upon installation, the circuit may not work at all
due to mislabelled pin-outs on terminating cable blocks and to flipflopped wires:
transmit-to-transmit as opposed to transmit-to-receive. These errors are
typically discovered upon circuit installation and possibly during circuit
acceptance when tests are performed end-to end.
3. Environmental:
Electrical storms, power lines,
electrical noise, interference, and crosstalk between transmission links can
cause logic errors, FAS (frame) errors, CRC errors in
addition to code errors. Typically, these conditions cause intermittent, bursty
errors, which are some of the most difficult to locate.
4. Data
Specific: Data characteristics, such as
repetitive patterns, can force equipment to create pattern-dependant jitter and
code errors. These errors may not exist when testing the transmission path with
standard pseudorandom patterns.
Analyzing
2.048 Mbps Impairments - Techniques and Measurements
Analyse a 2.048 Mbps circuit’s performance
and to isolate the causes of degraded services, the test set must perform many measurements
in different scenarios. There are four typical scenarios where 2.048 Mbps
testing is required:
1.
Installation:
When installing a 2.048 Mbps
circuit, out-of-service testing is very useful in verifying equipment operations
and end-to-end transmission quality. One starts by testing the equipment (such
as NTE’s, channel banks, multiplexers), and then verifying cable connections, timing
source selections, and frequency outputs. Application #2 covers this test scenario.
2.
Acceptance
Testing: In addition to the test performed
during installation, two other tests—stress tests and timed tests—
should be performed to ensure that the 2.048 Mbps
circuit is operating properly with respect to the relevant 2.048 Mbps
circuit specifications and tariff. The equipment may be
stressed by verifying the transmission frequency around 2.048 Mbps equipment.
The same procedure may be performed end-to-end to stress the entire 2.048 Mbps
circuit. Timed tests with printouts should be performed over a 24- or 48-hour
period using standard pseudorandom patterns, which simulate live data. Application #2 is useful for this scenario.
3.
Routine Preventive Measure: Routine maintenance test are strongly recommended once
live data is transmitted across the 2.048 Mbps circuit. Routine maintenance can
alert technicians to degrading service before it disrupts normal operations. In
most instances, this involves monitoring the live data for alarms, code errors,
FAS (frame) errors, CRC errors, and signal frequency
measurements
which provide information about the performance of the 2.048 Mbps circuit.
These tests should be performed
with
printouts over a 24- or 48-hour period to detect time specific or intermittent
errors. Application #1 covers this scenario.
4.
Fault Isolation: Fault isolation is required once service is disrupted
due to excessive error rates. This can be performed using both in-service and
outof- service tests. In-service monitoring provides general information and
can be used before out-of-service analysis to localise problems and minimise circuit
downtime. By monitoring the circuit at various points, technicians are able to
analyse
the results and determine where problems are originating. By performing standard
out-of-service tests, such as loopback and end-to-end tests, technicians are
able to stress the equipment, find sources of errors, and verify proper operation
once the trouble is repaired. Application
#1 and Application #2 are relevant for fault
isolation.
Application #1:
In-Service Analysis of
Live Traffic
The
following
sections explain how to evaluate the performance of a2.048 Mbps system using customer
data. It is useful:
• When performing
periodic maintenance and when looking for transmission degradation before it
effects service.
• When analysing the
span for intermittent errors, which are caused by faulty equipment or
environmental influences.
• For analysis of
2.048 Mbps circuits which cannot be taken out-of-service.
Figure 6:
Possible 2.048 Mbps
circuit monitoring
Table 3:
Common alarm and
error indications (in-service testing)
• Before
out-of-service analysis, to localise the problem and minimize circuit downtime.
To
achieve all these benefits, the test set may be configured to monitor the 2.048
Mbps circuit from practically any 2.048 Mbps access point.
Figure 6 shows a typical
circuit and possible monitoring locations.
Analysis of Alarm and
Error Indications (In-Service Testing)
Testing and
troubleshooting of a 2.048 Mbps signal requires regular monitoring for alarms
and errors. The
monitoring for alarms
and errors allows the user to detect and sectionalize transmission lines or
equipment problems in a 2 Mbps signal. Errors can also be intentionally injected
to see the response of the system.
Table 3 highlights some of
the important alarm and error indications along with possible reasons and
solutions.
The AIS and FAS Distant
Alarms
This section gives a
detailed explanation of the 2.048 Mbps AIS and FAS Distant alarms.
The AIS Alarm
An AIS alarm is an
unframed continuous stream of binary ones. However, a signal with all bits
except the frame alignment in the 1 state is not mistaken as an AIS. If the
network equipment shown in Figure 7 suffers a signal or frame synchronisation
loss, or receives an AIS alarm at input #1(2), it transmits the AIS
alarm at output #1(2).
Hence, the AIS alarm indicates the presence of an alarm indication to the
equipment farther downstream (away from the source of the trouble).
Therefore if the test
set receives an AIS alarm, this indicates that the trouble must lie somewhere
farther upstream in the network. This is illustrated in Figure 8.
The FAS Distant alarm
is indicated by setting bit 3 equal to 1 in time slot 0 of the frames not
containing the FAS pattern. (See Figure 3 on page 4). If the
network equipment shown in Figure 9 suffers a signal or frame synchronisation
loss, or receives an AIS alarm at input #1(2), it transmits the FAS Distant Alarm
at output #2(1). Hence, the FAS Distant alarm indicates the presence of an
alarm condition to the equipment farther upstream (back towards the source of
the trouble). Therefore if the test set receives a FAS Distant alarm, this
indicates that the trouble must lie somewhere farther downstream in the
network. This is illustrated in Figure 8.
Code Error Analysis
The bipolar nature of
the AMI signal allows the detection of single (isolated) errors since single
errors on
the line cause a
pulse to be either incorrectly added or omitted, which in turn results in two
successive pulses of the same polarity. This constitutes a violation of the
bipolar coding scheme. Recall that due to the zero suppression scheme used in
HDB3, the signal may also contain intentional bipolar code violations
representing strings of 4 consecutive zeros. These intentional code violations due
to HDB3 must be distinguishing from code violations due to the errors occurring
on the 2.048 Mbps line. Since bipolar
code violations due to HDB3 follow specific rules, they can be recognised as
such by the test set. This constitutes the basis for the
code error analysis performed by the test set.
A code error is
defined as any violation of the bipolar code, which is not a code violation due
to HDB3’s zero substitution algorithm. For comparison, an illustration of a
code error along side an HDB3 substitution code is shown in Figure 9.
It is not necessary to receive and transmit a known pattern to recognise code errors.
Hence the test set can perform code error analysis on an
in-service basis without disrupting the traffic on the 2 Mbps line. To do this
analysis, the test set provides the following key result:
Advantages/Limitations
of Code Error Analysis
Code errors provide
an approximate indication of the error performance on a metallic 2.048
Mbps line without the need to disrupt live traffic. Furthermore, they can generally
be used to sectionalise problems
to the local span in
the 2.048 Mbps network. (This will be discussed further under “Correlation of
Results and Problem Causes”). It must be noted, however, that code error
analysis has certain limitations. Code
errors are useful in
identifying local (near end) metallic span and repeater problems. However they
are not a good indication of end-to-end performance since network equipment
beyond the local span or nonmetallic transmission media (e.g. microwave and
fibre) will correct code errors in the far end 2.048 Mbps span.
FAS (Frame Alignment Signal)
Error Analysis
As we explained in
our discussion of the 2.048 Mbps Framing Format, time slot 0 of every other
2.048 Mbps frame contains a fixed 7-bit long FAS pattern (See Figure
3 on page 4). When doing in-service FAS error analysis, the test
set takes advantage of the fact that even though the data portion of the 2.048
Mbps frame is unknown, the FAS bits contain a known pattern such that
the errors occurring on these bits can be detected without disrupting the
traffic.
Hence the test
set counts a FAS error each time one or more bits in the FAS pattern are
received in error. Upon synchronisation with the frame alignment signal, the test set
automatically provides the following result:
Advantages/ Limitations
of FAS Error Analysis
FAS errors allow
in-service error performance analysis of the 2.048 Mbps circuit. Under random
(Gaussian) error conditions, the FAS error rate will closely approximate the
actual error rate if the test is performed over a significantly long period of
time. Moreover FAS errors can be used to isolate problems to network equipment (such
as digital cross connect systems and higher order multiplexers) which frame
(or reframe) the
2.048 Mbps data. The limitations of FAS error analysis are threefold. 1. Since the FAS
pattern takes up only 7 bits for every 512 bits transmitted (2 frames x 32 time
slots/frame x 8 bits/time slot = 512 bits), the analysis is performed on a relatively
small number of the received bits (about 1.4%). As a result, errors not occurring
on the FAS bits will be missed. 2. Bursty error condition are far more common
than random (Gaussian)
error condition. 3.
FAS errors are corrected by multiplexers and digital cross-connected systems. Hence,
FAS error analysis cannot be used to determine end-to-end error performance in
networks where this type of equipment is installed.
CRC Error Analysis
When the 2.048 Mbps
signal has the CRC Multiframe format implemented, the test
equipment will automatically perform CRC error analysis as explained in Table
4.
Advantages/Limitations
of CRC Error Analysis
Most data sequences
generate a CRC word which can be uniquely associated with that particular data
sequence. Therefore, CRC errors can detect the presence of one or more bit
errors in a submultiframe to a very high degree of accuracy (93.75%) without
the need to take the 2.048 Mbps circuit out-of-service.
However, the
following limitation of CRC error analysis must be kept in mind.
1. A CRC error
indicates the occurrence of one or more errors, but not the total number
of errors in a submultiframe.
Hence, the BER
obtained using the formula above will be somewhat lower then the actual error
rate if the error rate
is so high that there
are several errors in the submultiframe.
1
error per submultiframe corresponds to an average error rate of 4.9E-4.
2. CRCs may be
recalculated by network equipment such as digital cross connect systems.
Therefore, CRC error analysis cannot be used to determine end-to-end performance
in networks where this type of equipment in installed.
Correlation of In-Service
Results
To find possible
problem causes, use Figure 10 to find your location along the 2.048
Mbps span, and cross-reference your location with Table 5, which
shows various combinations of the results discussed in the previous sections.
Application
#2:Out-of-Service Testing of 2.048 Mbps Circuits
The following
sections explain how the test set is used to evaluate the performance
of a 2.048 Mbps
system using
pseudorandom data. It is useful:
• When installing
2.048 Mbps circuits and verifying end-to-end continuity.
• When isolating 2.048
Mbps circuit faults and verifying end-to-end continuity.
• When performing
acceptance testing which includes timed and stress tests.
Errors found via this
analysis may be caused by faulty equipment, improper connections, environmental
influences, or data content. To find these errors, use results such as bit
errors, bit error rate (BER), FAS
errors, pattern
slips, received frequency, error free seconds (EFS), percentage error free seconds
(%EFS), etc, which are all measured simultaneously. These results will help in isolating
the cause of the problem. There are basically two methods of performing
out-of-service testing: loopback testing and end-to-end testing. These methods are
addressed in the following sections.
Analysis of Alarm and
Error Indications (Out-of-Service Testing)
Testing and
troubleshooting of a 2.048 Mbps signal requires regular monitoring for alarms
and errors. The
monitoring for alarms
and errors allows the user to detect and sectionalize transmission lines or
equipment problems in a 2 Mpbs signal. Errors can also be intentionally injected
to see the response of the system.
Table 6 highlights some of
the important alarm and error indications along with possible reasons and
solutions.
Table 6:
End-to-End Testing
End-to-end testing is
performed with two test sets so that both directions of the 2.048
Mbps circuit may be analysed simultaneously. Figure 11 shows the
set-up of an end-to-end test. This test method is
better then the
loopback test since the direction of errors can be found more quickly.
Loopback Testing
Loopback testing is
performed with one test set. Figure 12 shows the
set-up of the loopback test. If NTE loopbacks are established to perform the
test, it is important to realise that the far end NTE in loopback will affect
the result. By design, most NTE’s remove received code errors before transmitting
the data. This will affect the analysis result, because the near end technician
will be unaware of code errors occurring on the far end metallic loop and may
draw inconclusive results. Furthermore loopback tests cannot identify incorrect
timing configurations where the customer premises equipment (connected to the
NTE) may not be loop-timed to the network. The appropriate pseudorandom pattern
recommended for out-of-service testing at 2.048 Mbps is the 215 Ð 1 pattern as
specified by ITU-T Recommendation O.151.
A pattern slip is the
insertion of data bits into or from the data stream. Based on the source of the
slip and its effect on the network, all slips can be placed on any of the following
categories.
1. Controlled Slips:
Controlled Slips are bit additions or deletions which do not disrupt frame
synchronisation. These
slips are typically caused by synchronisation impairments in digital cross-connect
(DCS) equipment. DCS
equipment handles
buffer overflows or underflows by deleting or repeating entire frames of data.
Since data is added or deleted by entire frames, frame synchronization is not
disrupted.
2. Uncontrolled Slips:
Uncontrolled slips are bit additions or deletions that cause both data and
framing bits to be displaced. The misalignment of framing bits typically results
in frame synchronisation loss. Uncontrolled slips are typically from synchronisation
problems in equipment which buffer the entire bit stream such as satellite down
link receivers. Since the buffer in this equipment does not distinguish between
framing and data bits, buffer underflows or overflows result in the addition
and deletion of arbitrary blocks of data.
It should be noted
that slips can also result from impairments unrelated to network synchronisation.
Low signal level, noise, and excessive jitter can also cause slips. Examples of
controlled and uncontrolled slips are illustrated
in Figure 13.
Measuring the Slips
The test
sets pattern slip measurements count the number of times data is inserted into
or deleted from the pattern. This measurement is not a count of the actual
number of bits added or deleted, but rather a count of the number of instances
where a group of bits were added or deleted from the bit stream.
Interpreting the
Results
To troubleshoot a
problem, which causes slips, pattern slip results must be compared to other
test results.
If an occurrence of a
pattern slip is associated with a frame loss, it can be assumed that the frame
loss is caused by an uncontrolled slip. If a pattern slip occurs without
disrupting framing, it can be assumed that a controlled slip has occurred. Categorization
of slips can help identify the cause of the problem.
A better
understanding of the underlying problems can also be obtained by considering
the frequency at which pattern slips
Transmission Delay
Analysis
Using the test
set’s DELAY can help in troubleshooting specific problems such as protocol
errors due to timeouts.
Figure 14:
Roundtrip delay
measurements
As an example
consider the 2.048 Mbps circuit shown in Figure 14. In this
figure, transmission path #1 has a roundtrip delay of 30 ms, whereas transmission
path #2 has a round trip delay of 75 ms. If we assume a protocol timeout
threshold of 50 ms, switching the 2.048 Mbps circuit from transmission path #1
to transmission path #2 would cause protocol timeouts not experienced when path
#1 was in use. test set’s DELAY measurements can identify
this problem by determining such changes in the transmission path of a 2.048
Mbps circuit.
ITU-TPerformance
Analysis
Performance Analysis
results as specified by ITU-T Recommendations G.821 provide statistical
information about the performance of the equipment or system under test. These
results are used to check the compliance of equipment or circuits with the
specified performance objectives.
Available Time vs. Unavailable
Time
According to ITU-T
Recommendation G.821, the total test time after the initial pattern
synchronisation is broken up into available and unavailable seconds. Every test
second belongs to either one of these categories. This is illustrated in Figure
15. After initial synchronisation is achieved, seconds are considered
to be available time. When the bit error rate (BER) is worse then 10-3 for 10 consecutive
seconds, a transition is made to unavailable time, and these 10 seconds are
considered to be unavailable time. When the BER is better then 10-3 for 10 consecutive
seconds, the period of unavailable time terminates, and these 10 seconds are counted
as available seconds. Hence, a sliding window, 10 seconds in length, is used to
detect transitions from available time to unavailable time and vise versa.
Any second in which a
signal loss or pattern synchronization loss occurs, is also considered to be a
second with BER worse then 10-3.
Available Time
As shown in Figure
16, available time (or available seconds) is broken up into further categories.
These categories are explained below. Severely errored seconds are defined to
be part of available time. Therefore, severely errored seconds are likely to
account for short error bursts with a BER worse then 10-3, whereas longer error
bursts with a BER worse then 10-3 are
likely to be counted as part of unavailable time. Error Free Seconds Available
seconds (EFS) in which no bit errors occurred. Errored Seconds Available
seconds (ERR SEC) in which at least one bit error occurred. Severely Errored
Available seconds Seconds (SES) in which the BER was worse than 10-3.
Severely errored
seconds are defined to be part of available time. Therefore, severely errored seconds
are likely to account for short error bursts with a BER worse then 10-3, whereas longer error
bursts with a BER worse then 10-3 are
likely to be counted as part of unavailable time.
Degraded Minutes
Degraded minutes is a
count of the number of minutes during which an average BER of 10-6 or worse occurs. The
one-minute intervals are derived by removing unavailable seconds and severely
errored seconds from the total test time, and then consecutively grouping the
remaining seconds into blocks of 60. The average BER is calculated for the block
of 60 seconds, and if it is 10-6 or
worse, the block is counted as a degraded minute.
